1. Field of the Invention
The present invention generally relates to the field of data communications and data processing architectures. More particularly, the present invention relates to a high speed memory interface for an external random access memory device.
2. Description of Related Art and General Background
The unprecedented growth of data networks (e.g., corporate-wide Intranets, the Internet, etc.) as well as the development of network applications (e.g., multimedia, interactive applications, proprietary corporate applications, etc.) have resulted in creating a demand for higher network bandwidth capabilities and better network performance. Moreover, such demands are exacerbated by the advent of policy-based networking, which requires more data packet processing, thereby increasing the amount of work per packet and occupying processing resources. One approach to increase network bandwidth and improving network performance is to provide for higher forwarding and/or routing performance within the network.
Some improvements in routing performance are directed to enhancing processor throughput. Processor designers have been able to obtain throughput improvements by greater integration, by reducing the size of the circuits, and by the use of single-chip reduced instruction set computing (RISC) processors, which are characterized by a small simplified set of frequently used instructions for rapid execution. It is commonly understood, however, that physical size reductions cannot continue indefinitely and there are limits to continually increasing processor clock speeds.
Further enhancements in processor throughput include modifications to the processor hardware to increase the average number of operations executed per clock cycle. Such modifications, may include, for example instruction pipelining, the use of cache memories, and multi-thread processing. Pipeline instruction execution allows subsequent instructions to begin executing before previously issued instructions have finished. Cache memories store frequently used and other data nearer the processor and allow instruction execution to continue, in most cases, without waiting the full access time of a main memory. Multi-thread processing divides a processing task into independently executable sequences of instructions called threads and the processor, recognizing when an instruction has caused it to be idle (i.e., first thread), switches from the instruction causing the memory latency to another instruction (i.e., second thread) independent from the former instruction. At some point, the threads that had caused the processor to be idle will be ready and the processor will return to those threads. By switching from one thread to the next, the processor can minimize the amount of time that it is idle.
In addition to enhancing processor throughput, improvements in routing performance may be achieved by partitioning the routing process into two processing classes: fast path processing and slow path processing. Partitioning the routing process into these two classes allows for network routing decisions to be based on the characteristics of each process. Routing protocols, such as, Open Shortest Path First (OSPF) and Border Gateway Protocol (BGP), have different requirements than the fast-forwarding Internet Protocol (FFIP). For example, routing protocols, such as OSPF and BGP, typically operate in the background and do not operate on individual data packets, while FFIP requires IP destination address resolution, checksum verification and modification, etc. on an individual packet basis.
The IP fast forwarding problem is becoming harder as the amount of time allotted for processing on a per packet basis steadily decreases in response to increasing media transmission speeds. In an effort to alleviate this problem, many router and Layer-3 switch mechanisms distribute the fast path processing to every port in their chassis, so that fast path processing power grows at a single port rate and not at the aggregate rate of all ports in the box. This provides only temporary relief as network wire speeds have increased exponentially recently (e.g., Ethernet's 10, 100, to 1,000 MBps increase) while processing speeds have traditionally improved, on average, by a factor of two every 18 months. It is clear that most of current solutions will run out of steam, as the faster media become the mainstream.
There are a number of integrated circuit memories commercially available. For example, dynamic memory circuits having memory cells arranged to be accessed in a random fashion are referred to as dynamic random access memories, DRAMs. These memories can be produced in a variety of designs which provide different methods of reading from and writing to the dynamic memory cells. One such method is page mode operations. Page mode operations in a DRAM are defined by the method of accessing a row of a memory cell array and randomly accessing different columns of the array. Data stored at the row and column intersection can be output while that column is accessed.
An alternate type of memory access is the extended data output (EDO) memory which allows data stored at a memory array address to be available as output after the addressed column has been closed. Yet another type of operation is included in a burst EDO memory which adds the ability to address one column of a memory array and then automatically address additional columns in a pre-determined manner without providing the additional column addresses on external address lines.
Clocked synchronous memory, such as synchronous static random access memory (SSRAM) and synchronous dynamic random access memory (SDRAM) utilize a free running clock in order to perform transfers of data. In such a configuration, the clock continues to run without interruption as long as power is applied to the system. Each clocked synchronous memory accepts a free running clock signal on a clock input.